

The Sparc Back End
The Sparc back end can function in two different modes:
 Sparc V8
 This is V8 instruction set is used. In this mode the processor
behaves like a 32bit processor. In this mode we assume we
have 16 floating point registers numbered %f0, %f2, %f4, ..., %f30.
These are all in IEEE double precision.
 Sparc V9
 This generates code assuming the V9 instruction set is used.
In this mode the processor functions at 64bit. In this mode the
floating point processors can number from %f0, %f2, %f4, ..., %f62.
These are all in IEEE double precision.
New V9 instructions include the 64bit extended version of multiplications,
divisions, shifts, and load and store.
MULX SMULX DIVX SLLX SRLX SRAX LDX STX
Also, V9 includes conditional moves and more general form of branches.
 MOVcc
 conditional moves on condition code
 FMOVcc
 conditional moves on condition code
 MOVR
 conditional moves on integer condition
 BR
 branch on integer register with prediction
 BP
 branch on integer condition with prediction
General Setup for V8
The SPARC architecture has 32 general purpose registers
(%g0 is always 0)
and 32 single precision floating point registers.
Some Ugliness: double precision floating point registers are
register pairs. There are no double precision moves, negation and absolute
values. These require two single precision operations. I've created
composite instructions FMOVd,
FNEGd and
FABSd to stand for these.
All integer arithmetic instructions can optionally set the condition
code register. We use this to simplify certain comparisons with zero
in the instruction selection process.
Integer multiplication, division and conversion from integer to floating
go thru the pseudo instruction interface, since older sparcs do not
implement these instructions in hardware.
In addition, the trap instruction for detecting overflow is a parameter.
This allows different trap vectors to be used.
General Setup for V9
Specializing the Sparc Back End


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Last modified: Thu Jan 9 19:38:15 EST 2003 by leunga@slinky

