MLRISC
MLRISC
Contributors
Requirements
How to Obtain MLRISC
Overview
Problem Statement
Contributions
MLRISC Based Compiler
MLRISC Intermediate Representation
MLRisc Generation
Back End Optimizations
Register Allocation
Machine Description
Garbage Collection Safety
System Integration
Optimizations
Graphical Interface
Line Counts
Systems Using MLRISC
Future Work
System
Architecture of MLRISC
The MLTREE Language
MLTree Extensions
MLTree Utilities
Instruction Selection
Assemblers
Machine Code Emitters
Delay Slot Filling
Span Dependency Resolution
The Graph Library
The Graph Visualization Library
Basic Compiler Graphs
The MLRISC IR
SSA Optimizations
ILP Optimizations
Optimizations for VLIW/EPIC Architectur...
Register Allocator
Back Ends
The Alpha Back End
The PA RISC Back End
The Sparc Back End
The Intel x86 Back End
The PowerPC Back End
The MIPS Back End
The TI C6x Back End
Basic Types
Annotations
Cells
Cluster
Client Defined Constants
Client Defined Pseudo Ops
Instructions
Instruction Streams
Label Expressions
Labels
Regions
Regmap

Optimizations


Optimizations
Register allocation
Scheduling for Superscalar Architecture...
VLIW Compilation
MLRISC assumes that all high level optimizations (target independent) have already been performed. This includes things like inlining, array dependence analysis, and array bounds check elimination. The target dependent optimizations that remain include register allocation, scheduling and traditional optimizations to support scheduling.

Register allocation

MLRISC includes a state-of-the-art graph-coloring based register allocator that has an aggressive algorithm for copy-propagation. The latter guarantees to eliminate copy instructions without introducing spills.

Spills in the register allocator are under the control of the client via call-backs to the front end. Where to spill registers and the associated information that must be maintained is client specific and varies with the compiler.

Scheduling for Superscalar Architectures

Several algorithms for acyclic global scheduling are provided. These include:

  • Superblock,
  • a variant of Bernstein/Rodeh, and
  • Percolation based scheduling.

These algorithms tend to be quite complex and require a large number of support data structures and analysis. These include data structures such as:

  • dominator/post dominator trees,
  • loop nesting tree,
  • control dependency graphs, and
  • data dependency graphs.

Support analysis and optimization include:

  • constant propagation,
  • global value numbering,
  • global code motion, and
  • loop invariant hoisting.

VLIW Compilation

MLRISC also contains a framework for the compilation of predicated VLIW architectures. Currently, the following algorithms have been implemented.
  • hyperblock formation
  • hyperblock scheduling
  • modulo scheduling

Lal George
Allen Leung
SML/NJ Validate this page
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Last modified: Thu Jan 9 19:38:15 EST 2003 by leunga@slinky