Register allocationMLRISC includes a state-of-the-art graph-coloring based register allocator that has an aggressive algorithm for copy-propagation. The latter guarantees to eliminate copy instructions without introducing spills.
Spills in the register allocator are under the control of the client via call-backs to the front end. Where to spill registers and the associated information that must be maintained is client specific and varies with the compiler.
Scheduling for Superscalar ArchitecturesSeveral algorithms for acyclic global scheduling are provided. These include:
These algorithms tend to be quite complex and require a large number of support data structures and analysis. These include data structures such as:
Support analysis and optimization include:
VLIW CompilationMLRISC also contains a framework for the compilation of predicated VLIW architectures. Currently, the following algorithms have been implemented.