Optimizations for VLIW/EPIC Architectures
Many newer architectures such as the upcoming IA-64 and the
DSPs such as the C6 are VLIW or so called EPIC machines.
These architectures depends on the compiler to
extract instruction level parallelism (ILP)
and data level parallelism (DLP).
Optimizations for these architectures include:
- Hyperblock construction
- Predication and predicate analysis
- Hyperblock scheduling
- Modulo scheduling
Last modified: Thu Jan 9 19:38:15 EST 2003 by leunga@slinky