G22.2243-001 - High Performance Computer Architecture - Spring 2006

Course Description Schedule Textbooks
Mailing List Resources Grading
Instructor: Dr. Mohammad Banikazemi  
E-mail: {my initals}@cs.nyu.edu
and {my initals}@us.ibm.com
Office: 401 WWH 
Office hours: W 7:00-8:00pm
Phone: 8-3081  

Semester: Spring 2006  
Time: Wed. 5:00 pm-7:00 pm 
Room:WWH 101
Course Web page: http://www.cs.nyu.edu/courses/spring06/G22.2243-001/index.html

Final exam: May 3, 5:00-6:50pm, WWH 101
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LecturesDateTopicHandouts ReadingsAssignments
11/18 Introduction
Fundamentals of Computer Design
Lecture 1
Chapter 1
21/25 Instruction Set Architecture
Basic Pileplining
Lecture 2
Chapter 2
Appendix A
Lab 0
32/1 Pipelining
Lecture 3
Chapter 2
Appendix A
HW 1 Due: 2/8
Lab 1 Due: 2/15
42/8 Branch Prediction
Lecture 4
Appendix A
Chapter 3
52/15 Branch Prediction
Dynamic Scheduling (Scoreboarding)
Lecture 5
Appendix A
Chapter 3
HW 2 Due: 2/22
Lab 2 Due: 3/1
62/22 Dynamic Scheduling (Tomasulo's)
Hardware Speculation and Superscalars
Lecture 6
Chapter 3
73/1 VLIW
Memory System: Cache
Lecture 7
Chapter 4
Chapter 5
HW 3 Due: 3/8
83/8 Memory System: Cache (Cont'd) Lecture 8
Chapter 5
Lab 3 Due: 3/29
93/22 Memory System: Main Meomory Lecture 9
Chapter 5
103/29 Multiprocessing
Snooping Protocol
Lecture 10
Chapter 6
HW 4 Due: 4/5
Lab 4 Due: 4/12
114/5 Multiprocessing
Directory Protocol
Lecture 11
Chapter 6
124/12 Interconnection Networks Lecture 12
Chapter 8
134/19 Case Studies
IBM and Intel Processors
Lecture 13
Handouts HW 5 Optional
Lab 5 Optional
144/26 Review
Practice problems
Lecture 14
The text book
Required reading
J. L. Hennessy, D. A. Patterson
"Computer Architecture: A Quantitative Approach," 3rd edition.
SimpleScalar Resources
Tools (from www.simplescalar.com)
Documentation (from www.simplescalar.com)

Sources (somewhat customized for NYU)
SimpleScalar simulator source (simplesim-3v0c.tgz)
This is common to both SPARC/Solaris and x86/Linux installations.

Department SPARC/Solaris machines (e.g., slinky, griffin, etc.)

x86/Linux installation
(README, simpletools-2v0-nyu.tgz , simpleutils-2v0-nyu.tgz)

Course Description
High Performance Computer Architecture is a graduate-level course which covers the design of advanced modern computing systems. In particular, the design of modern microprocessors, characteristics of the memory hierarchy, and issues involved in multi-threading and multi-processing are discussed. The main objective of this course is to provide students with an understanding and appreciation of the fundamental issues and tradeoffs involved in the design and evaluation of modern computers. Topics will include cost/performance analysis, design and evaluation of instruction set architectures, pipelining techniques, multi-level memory hierarchies, superscalar processor design, multi-threading and multi-processing. Through programming and analysis assignments students will build, in stages, a timing simulator for a simplified out-of-order multiple-issue microprocessor in order to examine the impact of various architectural techniques.
Grading policy
Final Exam30%
The course grade will be computed as follows: programming, analysis, and homework assignments (70%), final exam (30%).
The lecture slides used in this course are the slides developed and used by Prof. Vijay Karamcheti with some modifications. They have been derived from slides developed by Professors David Patterson and Randy Katz at the University of California, Berkely and Professor Michael Schulte at Lehigh University for their graduate Computer Architecture courses. The SimpleScalar assignments being used in this course were originally developed by Michele Co and Professor Kevin Skadron of the Computer Science Department at the University of Virginia. The instructor gratefully acknowledges all of their efforts.