V22.0436 - Prof. Grishman

Lecture 13: MIPS Processor Design: Building a Datapath

 
Text: Section 4.3

we will limit ourselves to a few instructions: lw, sw, beq, add, sub, and, or, slt (and later, j)

for simplicity in our initial design, we will assume separate memories for instructions and data; this will allow us to create a design which can read an instruction and then read or write data in a single cycle (text, Fig. 4.1)

Basic components

Building the data paths for the simple (single-cycle) implementation scheme (Fig. 4.5- 4.10)

Combining data paths

 To construct a complete data path for our machine, we need to combine these data paths, using multiplexers where necessary (Fig. 4.11).