G22.2243-001 - High Performance Computer Architecture - Fall 2007

Course Description Schedule Textbooks
Mailing List Resources Grading
Instructor: Prof. Mohammad Banikazemi  
E-mail: {my initals}@cs.nyu.edu
and {my initals}@us.ibm.com
Office: WWH 401 
Office hours: W 7:00-8:00pm
Phone: 8-3081  

Semester: Fall 2007  
Time: Wed. 5:00 pm-7:00 pm 
Room:WWH 402
Course Web page: http://www.cs.nyu.edu/courses/fall07/G22.2243-001/index.html

Final exam: TBD
Mailing List
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Tentative Schedule
LecturesDateTopicHandouts ReadingsAssignments
1 Introduction
Fundamentals of Computer Design
Lecture 1
Six-up
Chapter 1
2 Instruction Set Architecture
Basic Pileplining
Lecture 2
Six-up
Appendices B and A
HW 1
3 Pipelining
Lecture 3
Six-up
Appendix A
4 Branch Prediction
Lecture 4
Six-up
Appendix A
Chapter 2
Lab 0 Due: 10/03
5 Branch Prediction
Dynamic Scheduling (Scoreboarding)
Lecture 5
Six-up
Appendix A
Chapter 2
HW 2 Due: 10/10
Lab 1 Due: 10/17
6 Dynamic Scheduling (Tomasulo's)
Hardware Speculation and Superscalars
Lecture 6
Six-up
Chapter 2
Chapter 3
7 Memory System: Cache Lecture 7
Six-up
Chapter 3
Chapter 5
Lab 2 Due: 10/31
8 Memory System: Cache (Cont'd) Lecture 8
Six-up
Chapter 5
9 Memory System: Main Meomory
Multiprocessing
Lecture 9
Six-up
Chapter 5
HW 3 Due: 11/7
Lab 3 Due: 11/14
10 Multiprocessing Lecture 10
Six-up
Chapter 6
11 Multiprocessing
Interconnection Networks
Lecture 11
Six-up
Chapter 6
Lab 4 Due: 12/05
12 Interconnection Networks
13 Case Studies
IBM and Intel Processors
14 TBD
Textbook
Required reading
J. L. Hennessy, D. A. Patterson
"Computer Architecture: A Quantitative Approach," 4th edition.
Resources
SimpleScalar Resources
Tools (from www.simplescalar.com)
Documentation (from www.simplescalar.com)

Sources (somewhat customized for NYU)
SimpleScalar simulator source (simplesim-3v0c.tgz)
This is common to both SPARC/Solaris and x86/Linux installations.

Department SPARC/Solaris machines (e.g., slinky, griffin, etc.)
(README)

x86/Linux installation
(README, simpletools-2v0-nyu.tgz , simpleutils-2v0-nyu.tgz)

Course Description
High Performance Computer Architecture is a graduate-level course which covers the design of advanced modern computing systems. In particular, the design of modern microprocessors, characteristics of the memory hierarchy, and issues involved in multi-threading and multi-processing are discussed. The main objective of this course is to provide students with an understanding and appreciation of the fundamental issues and tradeoffs involved in the design and evaluation of modern computers. Topics will include cost/performance analysis, design and evaluation of instruction set architectures, pipelining techniques, multi-level memory hierarchies, superscalar processor design, multi-threading and multi-processing. Through programming and analysis assignments students will build, in stages, a timing simulator for a simplified out-of-order multiple-issue microprocessor in order to examine the impact of various architectural techniques.
Grading
Grading policy
Assignments70%
Final Exam30%
The course grade will be computed as follows: programming, analysis, and homework assignments (70%), final exam (30%).
Acknowledgement
The lecture slides used in this course are the slides developed and used by Prof. Vijay Karamcheti with some modifications. They have been derived from slides developed by Professors David Patterson and Randy Katz at the University of California, Berkely and Professor Michael Schulte at Lehigh University for their graduate Computer Architecture courses. The SimpleScalar assignments being used in this course were originally developed by Michele Co and Professor Kevin Skadron of the Computer Science Department at the University of Virginia. The instructor gratefully acknowledges all of their efforts.